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Role Description

• Develop test plans, writing testbenches and tests, and debugging any bugs found with the RTL team
• Develop and execute verification plans for digital designs using SystemVerilog and UVM
• Create and maintain testbenches, test cases, and test vectors
• Contribute to the development of novel methodologies and verification techniques
• Lead technical projects and mentorship of junior team members
• Run simulations to verify design against specifications. Analyze results, identify issues, and debug designs
• Implement coverage tracking and metrics
• Document plans, environments, test cases, and all results for a comprehensive record of all verification strategies

Qualifications

• BSEE/MSEE with 15+ years of hands-on experience in SoC verification using UVM
• Experience in Gate Level Simulation (GLS) setup and process corner failure analysis
• Experience using Cadence verification tools such as Xcelium, SimVision, and JasperGold
• Experience writing and debugging RTL using SystemVerilog
• Programming experience using C, C++, and/or Python/Perl
• Familiarity with digital design concepts and ASIC development flow

Requirements

• Experience verifying RISC-V based systems
• Experience with emulation or FPGA prototyping
• Experience with formal verification methodologies
• Familiarity with the Chisel hardware description language
• Experience verifying high-speed interfaces such as PCIe and DDR
• Experience with version control systems (e.g., Git) and Continuous Integration/Continuous Deployment (CI/CD) pipelines

Benefits

• Competitive salary scaled based on experience
• Bonus
• Stock
• Employer paid health care
• Employer contribution to health savings account
• Flexible time off
• Flexible work location with remote options
• 401K employer match