K2 Space

We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, R...

We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL ...

The Principal ASIC Design Verification Engineer will be responsible for developing and executing verification plans for various levels of silicon designs, building SystemVerilog/UVM test benches, and driving constrained-random and directed testing strategies. This role involves triaging simulation failures, ensuring coverage closure, managing regression testing, and supporting post-silicon validation.

The engineer will develop and execute verification plans for block, subsystem, and full-chip environments, building SystemVerilog/UVM test benches, assertions, and coverage models. Responsibilities also include driving testing strategies, running simulations, triaging failures, and ensuring coverage closure for sign-off.

The role involves developing and executing verification plans for various levels of silicon designs, building SystemVerilog/UVM test benches, and driving constrained-random testing strategies to validate functionality and corner cases. Responsibilities also include running simulations, triaging failures, managing regression testing, and participating in design reviews to influence design-for-verification best practices.

We are seeking a highly skilled Principal Digital ASIC Design Engineer to lead the design and implementation of digital subsystems for advanced wireless SoCs. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the...

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine S...

We are seeking a highly skilled Senior Mixed-Signal IC Design Engineer with strong expertise in high-speed data converter (ADC/DAC) and Phase-Locked Loop (PLL) design, particularly in advanced FinFET technology nodes. You will be part of a collaborative design team developing sta...

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine S...

The role involves designing and developing high-performance, high-speed ADC/DAC architectures and architecting low-power PLLs, frequency synthesizers, and clocking systems for state-of-the-art mixed-signal SoCs destined for satellites. Responsibilities span the full design lifecycle, including specification, modeling, simulation, verification, and supporting post-silicon bring-up and production.