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Role Description

We are seeking a highly skilled Senior Mixed-Signal IC Design Engineer with strong expertise in high-speed data converter (ADC/DAC) and Phase-Locked Loop (PLL) design, particularly in advanced FinFET technology nodes. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will architect, develop, and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have flown your sub-system in space and developed cutting-edge mixed-signal SoCs.

• Design and develop high-performance, high-speed ADC and DAC architectures.
• Architect and implement low-jitter, low-power integer-N and fractional-N PLLs, frequency synthesizers and clocking systems.
• Engage with cross-functional analog, digital, DV, firmware, SoC architecture, technology, packaging, silicon validation, production test, and manufacturing teams to implement circuits and sub-systems.
• Drive full lifecycle design including specification, modeling (Verilog-A/AMS), schematic design, simulation, post-layout verification, and silicon validation.
• Perform design optimization for power, area, and performance in advanced FinFET nodes.
• Develop and maintain design documentation and support post-silicon bring-up and characterization.
• Support your product through production and spaceflight.
• Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team.

Qualifications

• M.S. or Ph.D. in Electrical Engineering with a strong focus in analog/mixed-signal IC design.
• 5+ years of relevant industry experience in mixed-signal circuit design.
• Proven hands-on experience in high-speed ADC/DAC designs with deep understanding of architectures, performance metrics, and design trade-offs.
• Strong knowledge of PLL design principles, including charge pump, VCO, loop filter, multi-modulus divider, sigma delta modulator, and jitter analysis.
• Solid understanding of FinFET CMOS process characteristics and layout parasitic considerations.
• Proficient in EDA tools such as Cadence Virtuoso, Spectre, behavioral modeling (Verilog-A, Verilog-AMS, MATLAB), and similar tools.
• Strong debugging, problem-solving, and communication skills.

Requirements

• Familiarity with various RF transceiver architectures and their trade-offs, systems specifications, and ability to translate system requirements into circuit requirements.
• Tape-out experience in advanced FinFET nodes.
• Familiarity with digital calibration techniques and DSP-assisted mixed-signal systems.
• Solid understanding of and experience with building block circuits such as bandgaps, bias generators, TIAs, op-amps, filters, and LDOs.
• Exposure to EM/Reliability/ESD design best practices.
• Experience working in cross-functional, geographically distributed teams.

Benefits

• Base salary range for this role is $170,000 - $250,000 + equity in the company.
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level.
• Comprehensive benefits package including unlimited paid time off, medical/dental/vision coverage, life insurance, paid parental leave, and many other perks.