K2 Space Corporation

Building high powered satellites for a mass abundant future.

Principal Digital ASIC Design Engineer

Mechanical EngineerMechanical EngineerFull TimeRemoteTeam 11-50Since 2022H1B No SponsorCompany SiteLinkedIn

Location

United States

Posted

12 days ago

Salary

$190K - $285K / year

Bachelor Degree10 yrs expEnglish

Job Description

• Own the architecture, microarchitecture, RTL implementation, and integration of key digital blocks in wireless SoCs. • Collaborate with system architects to translate high-level DSP algorithms into efficient hardware implementations. • Drive end-to-end development of DSP systems (e.g., filters, beamformers, FFT/IFFT engines). • Convert chip specifications into RTL using internal IPs and external IPs. • Design and develop RTL for interfaces, power management, clocking, reset, test & debug. • Partner with analog/mixed-signal teams to define digital-analog interfaces, calibration engines, and control logic. • Optimize designs for power, performance, and area (PPA) and support timing closure through synthesis and backend collaboration. • Lead or contribute to verification planning and validation of complex digital subsystems. • Participate in chip bring-up and lab validation of complex digital subsystems. • Support your product through production and spaceflight. • Act as a technical leader and subject-matter expert, helping to teach, grow, and mentor others in the team.

Job Requirements

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years of relevant industry experience in digital ASIC design, with significant ownership of complex subsystems.
  • Proficiency in RTL design (SystemVerilog or Verilog), synthesis, and linting tools.
  • Experience in micro-architecture definition from architecture guideline and model analysis.
  • Experience in closing full-chip and subsystem timing working with synthesis and static analysis teams.
  • Experience with DFT tools for scan and BIST insertion.
  • Solid understanding of SoC design flows including clock/power domain crossing, timing constraints, and formal verification.
  • Experience developing and integrating DSP blocks for wireless communication (e.g. OFDM, MIMO, channel estimation, DFE, etc.).
  • Strong experience with EDA tools for design, synthesis, static timing analysis, and power analysis (e.g. Synopsys, Cadence, Siemens tools).
  • Strong debugging, problem-solving, and communication skills.

Benefits

  • Comprehensive benefits package including paid time off
  • Medical/dental/vision coverage
  • Life insurance
  • Paid parental leave
  • Many other perks

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