• Lead physical design team from synthesis to sign-off and tape-out • Run physical design tasks including synthesis and place-and-route • Work with digital design team to integrate analog and digital IP into design • Interact with design verification team and run verification tasks on design • Resolve DRC & LVS violations to produce DRC-clean GDS-II of chip to deliver to foundry • Interact with foundry partners through multi-party wafer and manufacturing runs • Interact with backend services partners on physical design tasks through sign-off • Implement and execute physical design management process with PD team • Setup and maintain physical design tools, primarily Synopsys, but also potentially including Mentor/Siemens EDA, Cadence, or ANSYS tools as necessary • Run power and energy modeling on synthesized, place-and-routed design • Interact with digital design team to resolve RTL-level issues leading to DRC violations • Mentor and train junior hardware physical design engineers