Advanced Packaging Engineer – Design & Signal Integrity

Who we are:

We are a stealth-mode startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors. The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver. Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.

What we need:

We are looking for an Electrical Engineer for ASIC Package Design & Signal Integrity to design, model, and validate advanced semiconductor packages to ensure high-speed data and power integrity, focusing on minimizing noise, reflections, and ensuring manufacturability for custom chips

Key tasks include running simulations (using tools like Ansys HFSS, Cadence Sigrity, ADS), defining package specifications, collaborating with IC designers and suppliers, analyzing power delivery networks (PDN), and debugging hardware for high-speed interfaces (UCIe,Ethernet).

Key Responsibilities:

• Package Development: Select and design optimal multi-die IC package types considering electrical performance, cost, and manufacturability.

• Signal Integrity (SI) Analysis: Perform pre- and post-layout simulations (e.g., eye diagrams, crosstalk) for high-speed interfaces (UCIe, D2D, high-speed serdes).

• Power Integrity (PI) Analysis: Model and simulate Power Delivery Networks (PDN) for low-voltage, high-current supplies, including AC/DC analysis and IR drop.

• Modeling & Simulation: Develop accurate simulation models (S-parameters, IBIS-AMI) for packages, PCBs, and sockets.

• Cross-Functional Collaboration: Work with IC design, physical design, board layout, and marketing teams to define requirements and resolve issues.

• Layout Review: Guide PCB/package layout, reviewing stack-ups, trace routing, and component placement for optimal SI/PI performance.

• Lab Validation: Support hardware bring-up, debug, and correlation between simulation/models and physical measurements.

• Technology Development: Research and implement new SI/PI techniques and tools for next-generation products.

Required Skills and Qualifications:

• B.S./M.S. in Electrical Engineering or related field.

• Strong understanding of EM theory, transmission lines, and signal integrity principles.

• Expertise in SI/PI simulation tools (Keysight ADS, Ansys HFSS, Cadence Sigrity/PowerSI).

• Experience with high-speed interfaces (UCIe, D2D, Ethernet).

• Knowledge of board materials, stack-up design, and constraint management.

• Hands-on experience with lab equipment (VNA, TDR, Oscilloscope).

• Proficiency in programming/automation (Python, Matlab) is a plus.

• Experience in Multi-Die package designs using standard UCIe (AP and/or SP)

• Experience selecting and managing sub-contractors

• Experience interfacing with TSMC for packaging options (bumping)

Compensation:

Target base salary for this role is $160,000 - $220,000 per year + meaningful equity + benefits + 401k. Our salary ranges are determined by role, level, experience, and location.

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