• responsible for the verification closure of entire projects, including design modules, sub-systems, and SoCs • drive a wide range of activities including test-planning, UVM based testbench development, regression and coverage closure • partner and collaborate with ASIC design, emulation, system hardware and post-silicon teams • define overall SOC level verification strategy, technical planning, direction • enable and drive the development of UVM environments to verify RTL at block, unit, and SoC levels • develop and execute functional tests according to verification test plans • instrument TB for functional and code coverage and drive to closure based on the coverage metrics • collaborate with cross-functional teams like design, software, emulation and silicon validation teams towards ensuring the highest design quality • guidance and leadership of team members • driving results via mentoring, coaching, and counseling • generation and enforcement of coding and verification guidelines