FortifyIQ
We offer a pre-silicon hardware design evaluation / protection software suite advancing side-channel attack resistance
Principal Verification Engineer
Location
United States
Posted
30 days ago
Salary
Not specified
Postgraduate Degree10 yrs expEnglishPerlPython
Job Description
• Lead verification planning and execution at the block and full-chip level.
• Partner with architects and designers to align verification goals with design intent.
• Build, enhance, and maintain UVM-based verification environments.
• Achieve and track coverage metrics to ensure complete functional validation.
• Collaborate with lab teams for silicon bring-up and debug.
• Drive verification methodology improvements and mentor team members.
Job Requirements
- MSEE with 10+ years or PhD with 7+ years of verification experience.
- Advanced knowledge of SystemVerilog and UVM methodology.
- Proficiency in EDA tools such as VCS, Xcelium, and IMC.
- Strong scripting and automation skills (Python, Perl).
- Excellent communication and leadership across cross-functional teams.
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