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Role Description

We are looking for an experienced ASIC Verification Engineer to support the verification of advanced AI-accelerated ASIC designs used in next-generation hardware platforms. This role focuses heavily on ARM-based IP verification and requires strong experience validating complex SoC components in advanced silicon environments. The selected candidate will work closely with a global engineering team responsible for ensuring the reliability and performance of high-efficiency silicon designs used in cutting-edge hardware technologies.

Key Responsibilities

• Lead and execute verification activities for ARM-based IP blocks within complex ASIC/SoC designs.
• Develop and maintain verification environments using System Verilog and UVM methodologies.
• Create and execute test plans, test cases, and regression suites to validate design functionality.
• Perform coverage analysis, debugging, and verification closure activities.
• Participate in design and architecture reviews related to ARM CPU, GPU, and debug components.
• Implement and maintain constraint-random and assertion-based verification techniques.
• Support gate-level simulation (GLS) and verification across multiple stages of the development lifecycle.
• Collaborate with cross-functional teams including design, architecture, and software teams to resolve issues and improve product quality.
• Contribute to improving verification processes, methodologies, and best practices across the engineering team.

Qualifications

• 5+ years of hands-on ASIC/SoC verification experience in semiconductor or hardware design environments.
• Strong expertise in System Verilog and UVM verification methodologies.
• Solid experience with ARM architecture and related IPs such as Cortex-A processors, Mali GPU, CoreSight, CSS600 or similar components.
• Experience with formal verification, assertions, constraint-random verification, and coverage-driven verification.
• Familiarity with coverage metrics, coverage analysis, and debugging complex hardware verification issues.
• Experience running gate-level simulations and verification performance validation.
• Ability to write and maintain C-based test programs for configuring and validating ARM IP blocks.
• Strong problem-solving skills and the ability to work independently in a highly technical environment.

Preferred Qualifications

• Exposure to advanced silicon nodes (5nm or smaller) is a plus.
• Experience working in large, distributed engineering teams.
• Knowledge of low-power ASIC design verification is advantageous.
• French language skills are beneficial but optional.

Benefits

• Quarterly travel to Paris for approximately 1 week based on project needs.
• Must work in EST time zone.
• 12 Months Contract.

Company Description

Join our team at MetaRPO and embark on a journey of growth and innovation.